TRAVEO™ T2G CYT2CL
The CYT2CL is a family of TRAVEO™ T2G microcontrollers dedicated to automotive systems such as cluster entry units. The family features an Arm® Cortex®-M4 CPU for primary processing and an Arm® Cortex®-M0+ CPU for peripheral and security processing.
The TRAVEO™ T2G CYT2CL family products contain embedded peripherals supporting controller area network with flexible data rate (CAN FD), local interconnect network (LIN), clock extension peripheral interface (CXPI), and LCD controller.
The devices are manufactured on an advanced 40-nm process. The TRAVEOTM T2G CYT2CL incorporates Infineon's low-power flash memory, and multiple high-performance analog, and digital peripherals, and enables the creation of a secure computing platform.
HMI Tool Certification Program
Infineon’s HMI Tool Certification Program is designed to provide our customers with the best experience when using HMI tools with our TRAVEOTM T2G Graphic Controllers. Partners who qualify for Infineon’s HMI Tool Certification undergo collaborative testing and assessment of their implementation of Infineon’s reference use-cases. learn more
Key features
- 160-MHz (max) 32-bit Arm® Cortex®-M4F CPU with
- 100-MHz (max) 32-bit Arm® Cortex®-M0+ CPU with
- Inter-processor communication in hardware
- Three DMA controllers
- Up to 4160 KB of code-flash with an additional 128 KB of work-flash
- Up to 512 KB of SRAM with selectable retention granularity
- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
- Secure boot and authentication
- AES: 128-bit blocks, 128-/192-/256-bit keys
- 3DES: 64-bit blocks, 64-bit key
- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic
- Curve (ECC)
- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data
- CRC supports CCITT CRC16 and IEEE-802.3 CRC32
- True random number generator (TRNG) and pseudo-random number generator (PRNG)
- Galois/Counter Mode (GCM)
- Memory protection unit (MPU)
- Shared memory protection unit (SMPU)
- Peripheral protection unit (PPU)
- Watchdog timer (WDT)
- Multi-counter watchdog timer (MCWDT)
- Low-voltage detector (LVD)
- Brown-out detector (BOD)
- Overvoltage detection (OVD)
- Clock supervisor (CSV)
Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash)
- Low-power Active, Sleep, Low-power Sleep, Deep Sleep, and Hibernate modes for fine-grained power management
- Configurable options for robust BOD
- Up to four pins to wakeup from Hibernate mode
- Wakeup recognition bit for each wakeup source
- Up to 128 GPIO pins to wakeup from Sleep modes
- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes
- Internal main oscillator (IMO)
- Internal low-speed oscillator (ILO)
- External crystal oscillator (ECO)
- Watch crystal oscillator (WCO)
- Phase-locked loop (PLL)
- Frequency-locked loop (FLL)
- Low-power external crystal oscillator (LPECO)
- Up to four LCD controllers, with 32 segments (SEG) and four commons (COM)
- Supports both Type A (standard) and Type B (low-power) drive waveforms
- Three drive modes:
- PWM drive at 1/2 bias
- PWM drive at 1/3 bias
- Digital correlation
- Operates in ACTIVE, SLEEP, and DeepSleep power modes
- Digital contrast control
- Two time-division multiplexing (TDM) interfaces
- Two pulse-code modulation-pulse width modulation (PCM-PWM) interfaces
- Up to five sound generator (SG) interfaces
- One PCM Audio stream mixer with five input streams
- Up to four CAN FD channels
- Up to 12 runtime-reconfigurable SCB (serial communication block) channels, each configurable as I2C, SPI, or UART
- Up to two independent LIN channels
- Up to two CXPI channels with data rate up to 20 kbps
- One SPI (single, dual, quad, or octal), xSPI interface
- On-the-fly encryption and decryption
- Execute-In-Place (XIP) from external memory
- Up to 46 16-bit and 16 32-bit timer/counter pulse-width modulator (TCPWM) blocks for regular operations
- Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSlee
- Year/Month/Date, Day-of-week, Hour: Minute: Second fields
- Supports both 12- and 24-hour formats
- Automatic leap-year correction
- Up to 140 Programmable I/Os
- Two I/O types
- GPIO Standard (GPIO_STD)
- GPIO Enhanced (GPIO_ENH)
- GPIO Stepper Motor Control (GPIO_SMC)
- High-Speed I/O Standard with Low Noise (HSIO_STDLN)
- Generates 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply
- Two types of regulators
- DeepSleep
- Core internal
- One SAR A/D converter
- The ADC also supports six internal analog inputs
- ADC supports addressing of external multiplexers
- ADC has a sequencer supporting autonomous scanning of configured channels
- One smart I/O block, which can perform Boolean operations on signals going to and from I/Os
- Up to eight I/Os (GPIO_STD) supported
- JTAG controller and interface compliant to IEEE-1149.1-2001
- Arm® SWD (serial wire debug) port
- Supports Arm® Embedded Trace Macrocell (ETM) Trace
- Data trace using SWD
- Instruction and data trace using JTAG
- GHS/MULTI or IAR EWARM for code development and debugging
- 144-LQFP, 16 × 16 × 1.7 mm (max), 0.4-mm lead pitch
- 144-LQFP, 20 × 20 × 1.7 mm (max), 0.5-mm lead pitch
- 176-LQFP, 24 × 24 × 1.7 mm (max), 0.5-mm lead pitch
- Infineon has a successful history of supporting various graphics applications in cars with displays.
- Infineon's TRAVEO™ T2G microcontrollers are designed to meet size constraints, reduce costs, and improve performance and bandwidth for car displays, compared to system-on-chip solutions.
In this training, you will get to know the TRAVEO™ T2G portfolio for body and graphics applications, its key features and safety functions, development kits, and finally TRAVEO™’s automotive software and tool partner ecosystem.