EZ-PD™ CCG7SC Single-port USB-C Power Delivery & DC-DC Controller

Overview

Highly Integrated USB PD and DC-DC controller for single and multiport charging applications

EZ-PD™ CCG7SC is a highly integrated single-port USB Type-C power delivery (PD) solution with DC-DC controller, complying with the latest USB-C and PD specifications and targeting single and multi-port consumer PD charging applications.

It comes with an on-chip 32-bit ARM® Cortex®-M0 MCU which allows the implementation of custom functions such as source policy management, load-sharing and system peripheral control using PWMs, I2C and SPI.

  • USB PD 3.1 SPR with PPS
  • ARM® Cortex®-M0 processor
  • 128 KB flash, 16 KB RAM, 32 KB ROM
  • Apple 2.4A, BC1.2, AFC, and QC5.0
  • High-side and buck-boost NFET drivers
  • Support buck and buck-boost config
  • Configurable DC-DC converters
  • VCONN FETs and HSCSA
  • Input voltage range: 5 V to 24 V with 40 V tolerance
  • CC and I2C firmware upgrade

  • USB-C multiport Charger and Adapter
  • USB-C docking downstream facing port
  • Wireless and PD charger
  • Cigarette lighter adapter (CLA)

EZ-PD™ CCG7SC is equipped with an ARM® Cortex®-M0 CPU which is a 32-bit MCU that has been optimized for low-power operation with extensive clock gating. It includes an interrupt controller (NVIC block) that has 32 interrupt inputs and a wakeup interrupt controller (WIC) that can wake the processor from deep sleep mode. EZ-PD™ CCG7SC devices have a 128-KB flash and 32-KB ROM for non-volatile storage. The ROM stores libraries for authentication and device drivers, such as I2C and SPI, saving flash space for user applications. The flash provides flexibility to store code for customer features and allows firmware upgrades to meet the latest USB PD specifications and application needs. The 16-KB RAM is used under software control to temporarily store the status of system variables and parameters. The device also has a supervisory ROM that contains boot and configuration routines.

The USB PD subsystem contains the USB PD physical layer block and supporting circuits. The physical layer or PHY consists of a transmitter and a receiver that exchange BMC-encoded data over the CC channel, following the PD 3.1 standard. All communication is half-duplex. The PHY uses collision avoidance techniques to minimize communication errors on the channel.

The USB PD block has all the required termination resistors (Rp and Rd) and switches required by the USB Type-C specification. Rp and Rd resistors are essential for implementing connection detection, plug orientation detection, and establishing the USB source/sink roles. Rp resistor functions as a current source. EZ-PD CCG7SC™ is fully compliant with revisions 3.1 and 2.0 of the USB PD specification. Additionally, the device supports PPS operation at all valid voltages between 3.3 V and 21 V.

  • Highly integrated and programmable single-port USB Type-C PD and DC-DC controller
  • Support USB PD 3.1 SPR, BC1.2, Apple Charging, Samsung AFC, QC5.0 fast charging standard
  • DC-DC support forced-buck and buck-boost configuration
  • DC-DC supports 150 kHz to 600kHz switching frequency
  • DC-DC supports FCCM and PSM mode
  • DC-DC support peak current cycle-by-cycle duty-limit control
  • Fault protection includes OVP, UVP, SCP, OTP, VCONN OCP, and VBUS-CC short
  • Support features such as dynamic load-sharing, cable compensation, black box, and firmware upgrade
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