Smart I/O™ (PDL)

The Smart I/O™ Component provides a programmable logic fabric interposed between a General Purpose Input/Output (GPIO) port and the connections to it from various peripherals and UDB sources.

Inputs to the chip from the GPIO port can be logically operated upon before being routed to the peripheral blocks and connectivity of the chip. Likewise, outputs from the peripheral blocks and internal connectivity of the chip can be logically operated upon before being routed to the GPIO port.

The programmable logic fabric of the Smart I/O Component can be purely combinatorial or registered with a choice of clock selection. Its functionality is completely user-defined and each path can be selectively bypassed if certain routes are not required by the fabric.

Each Smart I/O Component is associated with a particular GPIO port and consumes the port entirely. If the Component is not used, then the Smart I/O functionality for that port is bypassed.

The Component can operate down to Deep Sleep low-power mode and can wake up the chip using the port interrupt, when required.